1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method of fabricating a capacitor.
2. Description of the Related Art
A highly integrated memory device, e.g., dynamic random access memory (DRAM) with a storage capacity of 256 MB or above, needs to use a very thin dielectric layer in order to realize a three dimensional capacitance structure, such as a stack-type capacitor or a trench-type capacitor. These memory device should has enough storage charges to avoid the soft error. The dielectric layer is usually made from tantalum oxide (Ta.sub.2 O.sub.5), by a low pressure chemical vapor deposition (LPCVD) method. The dielectric constant of the tantalum oxide is larger than the dielectric constant of the oxide. The tantalum oxide has a dielectric constant of about 25 and the good step cover capability.
It is well known that the number of defects is inversely proportional to annealing temperature in the dielectric formation process, and that the quality of dielectric layer is directly proportional to the anneal temperature. However, a native oxide layer is formed at the interface between the dielectric layer and the bottom electrode in the high temperature annealing process. Hence the dielectric constant of the dielectric layer formed in subsequent processes is decreased by the formation of the native oxide layer, and the capacitance of the capacitor is decreased by the reduced dielectric constant. To the contrary, in a low temperature annealing process, the number of defects is not effectively reduced by the low temperature and the quality of the dielectric layer is decreased by this low temperature.
Conventionally, a hemispherical grained silicon (HSG) layer is formed to increase the surface area of the bottom electrode, but the surface of the HSG layer is sharp. Therefore, as the dielectric layer is formed in the subsequent process, the surface of the dielectric layer will be sharp. Therefore, the leakage current is caused by the sharp surface of the dielectric layer.
FIGS. 1A through 1D are cross-sectional views showing the progression of fabricating a capacitor structure according to a conventional method. Referring to FIG. 1A, a conductive layer 10 is provided. The conductive layer 10 serves to connect source/drain regions of transistors on a semiconductor substrate structure (not shown in the figures). Other device structures are already formed on the substrate structure. In order to simplify the figures and emphasize the characteristics of the conventional method, the substrate structure is not shown in the figures. The conductive layer 10 is formed, for example, by LPCVD method. For example, the conductive layer 10 is composed of doped polysilicon, Furthermore, the conductive layer 10 is utilized as a bottom electrode for the capacitor.
HSG layer 12 is then formed over the surface of the conductive layer 10. The HSG layer 12 is formed, for example, by using SiH.sub.4 and Si.sub.2 H.sub.6 as the reaction gases, and is carried out at a temperature of between the formation temperature of amorphous silicon and polysilicon. An annealing process is performed to improve the quality of the HSG layer 12. However, a thin layer of native oxide 13 is formed over the surface of the HSG layer 12 in the anneal process and the dielectric constant of the dielectric layer formed in subsequent processes is decreased by the native oxide layer 13. Therefore, the native oxide layer 13 will be removed in the subsequent processes.
Referring to FIG. 1B, the native oxide layer 13 over the surface of the HSG layer 12 is removed by the diluted hydrogen fluoride (HF) solution. Thereafter, a thin layer silicon oxynitride 14 (SiO.sub.x N.sub.y) is formed on the HSG layer 12 by a rapid thermal process (RTP). The RTP process is performed with nitrogen gas at a high temperature, so that a nitridation reaction occurs, forming the silicon oxynitride layer 14. The silicon atoms in the HSG layer 12 react with the nitrogen gas by the RTP process. The silicon oxynitride layer 14 is used as a barrier layer to prevent the formation of the native oxide in the subsequent thermal processes.
Referring to FIG. 1C, a tantalum oxide layer 16 is formed over the surface of the silicon oxynitride layer 14, for example, by a LPCVD method. The LPCVD method is performed by using Ta(OC.sub.2 H.sub.5).sub.5 compounds and is carried out at a temperature of about 360-480.degree. C. Thereafter, an anneal process is performed to density the tantalum oxide layer 16. The annealing process is performed with dry oxygen gases or nitrogen gases and is then raised to a temperature of about 700-950.degree. C. The tantalum oxide layer 16 is utilized as a dielectric layer for the capacitor. The formation of the native oxide is not effectively inhibited by the silicon oxynitride layer 14 formed according to the conventional method. In this manner, a native oxide layer 18 is formed at the interface between the tantalum oxide layer 16 and the silicon oxynitride layer 14 during the anneal process. Therefore, the dielectric constant of the dielectric layer and the capacitance of the capacitor are decreased by the native oxide layer 18.
In addition, FIG. 1C shows that the surfaces of the HSG layer 12 and the tantalum oxide layer are sharp, as shown in regions 19. This causes leakage current to form in the regions 19.
Referring to FIG. 1D, a layer of top electrode composed of titanium nitride (TiN) is formed over the surface of the tantalum oxide 16, for example, by a sputtering method.
Subsequently, conventional processes for the complete formation of the capacitor are performed. Because the conventional processes are familiar to those skilled in the art, detailed descriptions are omitted here.
The formation of the native oxide layer 18 is not inhibited by the silicon oxynitride layer 14 in the conventional processes. Therefore, the dielectric constant of the dielectric layer and the capacitance of the capacitor are reduced by this native oxide layer 18. The annealing temperature is limited by the formation of the native oxide layer 18. Hence the quality of the dielectric layer is decreased. Furthermore, leakage current effect of the capacitor is caused by the sharp surface of the dielectric layer.